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Preliminary
RF2461
CDMA/FM LOW NOISE AMPLIFIER/MIXER 900MHZ DOWNCONVERTER
8
Typical Applications
* CDMA/FM Cellular Systems * Supports Dual-Mode AMPS/CDMA * Supports Dual-Mode TACS/JCDMA
* General Purpose Downconverter * Commercial and Consumer Systems * Portable Battery-Powered Equipment
Product Description
The RF2461 is a receiver front-end designed for the receive section of dual-mode CDMA/FM cellular applications. It is designed to amplify and downconvert RF signals, while providing 30dB of stepped gain control range. Features include digital control of LNA gain, mixer gain, and power down mode. Another feature of the chip is adjustable IIP3 of the LNA and mixer using an off-chip current setting resistor. Noise figure, IP3, and other specs are designed to be compatible with the IS-98B interim standard for CDMA cellular communications. The IC is manufactured on an advanced Silicon Germanium HBT process and is in a 4mmx4mm, 20-pin, leadless chip carrier.
1.00 0.90 0.60 0.24 typ
4.00 sq.
4 PLCS
0.65 0.30
3
0.20
2.10 sq.
12 MAX 0.05
Dimensions in mm.
0.75 0.50 0.50 Note orientation of package. 0.23 0.13
4 PLCS
NOTES: 1 Shaded lead is Pin 1. 2 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional.
8
FRONT-ENDS
3 Dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 4 Package Warpage: 0.05 mm max. 5 Die Thickness Allowable: 0.305 mm max.
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS
Package Style: LCC, 20-Pin, 4x4
uSiGe HBT
ENABLE IP SET IF SEL 20 19 18
GaAs HBT
GaAs MESFET Si CMOS
VCC2 LO IN
Features
* Complete Receiver Front-End * Stepped LNA/Mixer Gain Control * Adjustable LNA/Mixer Bias Current * Adjustable LNA/Mixer IIP3 * Meets IMD Tests with Three Gain States/
17
16
LNA GAIN
1
15
IF2+
MIX GAIN
2
14
IF2-
LNA IN
3
13
BYPASS
Two Logic Control Lines
VCC1 4 12 IF1+ GND1B 5 11 IF1-
6 LNA OUT
7 ISET2
8 ISET1
9 GND3B
10 MIX IN
Ordering Information
RF2461 RF2461 PCBA CDMA/FM Low Noise Amplifier/Mixer 900MHz Downconverter Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA
Rev A13 010607
8-123
RF2461
Absolute Maximum Ratings Parameter
Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature
Preliminary
Rating
-0.5 to +5.0 +6 -40 to +85 -40 to +150
Unit
VDC dBm C C
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Specification Min. Typ. Max.
Unit
Condition
T = 25C, VCC =3.0V CDMA: RF=880MHz, IF=85MHz, LO=965MHz@-10dBm JCDMA: RF=851MHz, IF=110MHz, LO=741MHz@-4dBm
Overall
RF Frequency Range LO Frequency Range IF Frequency Range 800 700 0.1 13.5 +7.0 14.5 1.8 +9.0 5 -6 +18.0 0 15 1.8 +11.0 6.5 -7 +24.0 0 16 2 869 to 894 832 to 870 954 to 979 722 to 760 1000 1000 250 15 2 MHz MHz MHz dB dB dBm mA dB dBm mA dB dB dBm mA dB dBm mA
LNA - CDMA
Gain Noise Figure Input IP3 Current
8
FRONT-ENDS
IIP3 is adjustable. VIPSET =0V
LNA Bypass - CDMA
Gain Input IP3 Current -8 +16.0
LNA - JCDMA
Gain Noise Figure Input IP3 Current 14 +9.0
IIP3 is adjustable. VIPSET =3V
LNA Bypass - JCDMA
Gain Input IP3 Current -9 +20.0
Mixer - High Gain Mode CDMA
Gain Noise Figure Input IP3 RF to IF Isolation Current (including LO Buffer/Bias) 13 +3.0 14.5 5.5 +4.0 7 dB dB dBm dB mA
3k balanced load.
IIP3 is adjustable. Decreasing R4/R5 will increase IIP3.
21
Mixer - Low Gain Mode CDMA
Gain Noise Figure IIP3 RF to IF Isolation Current (including LO Buffer/Bias) 4 +13.0 5.8 13 +14.0 18 14 dB dB dBm dB mA
8-124
Rev A13 010607
Preliminary
Parameter
Mixer - High Gain Mode JCDMA
Gain Noise Figure Input IP3 Current (including LO Buffer/Bias) 12 +2.0 13 5.5 +3.0 24 7 dB dB dBm mA
RF2461
Specification Min. Typ. Max. Unit Condition
3k balanced load.
IIP3 is adjustable. Decreasing R4/R5 will increase IIP3.
Mixer - Low Gain Mode JCDMA
Gain Noise Figure IIP3 Current (including LO Buffer/Bias) 2.5 +10.0 4.0 13 +12.0 21 14 dB dB dBm mA
Local Oscillator Input
Input Level LO to IF Isolation LO to LNA Isolation -10 -70 -60 dBm dB dB
Cascade LNA High/Mixer High
Gain Noise Figure Input IP3 Current 23.5 -11 26 2.4 -9 26 28 0 dB dB dBm mA
Any gain state. LNA High Gain/Mixer High Gain. Assumes 3dB Image filter insertion loss.
8
FRONT-ENDS LNA High Gain/Mixer Low Gain. Assumes 3dB Image filter insertion loss.
Cascade LNA High/Mixer Low
Gain Noise Figure Input IP3 Current 16.5 4.9 0 23 dB dB dBm mA
Cascade LNA Low/Mixer High
Gain Noise Figure Input IP3 Current 4 15.5 11.8 22 dB dB dBm mA
LNA Low Gain/Mixer High Gain. Assumes 3dB Image filter insertion loss.
Cascade LNA Low/Mixer Low
Gain Noise Figure Input IP3 Current -7 +14 -4.5 22.5 +20 18 3.0 -3 40 dB dB dBm mA V
LNA Low Gain/Mixer Low Gain. Assumes 3dB Image filter insertion loss.
Power Supply
Voltage 2.65 3.15
Rev A13 010607
8-125
RF2461
Pin 1 Function LNA GAIN Description
Controls the bypass feature of the LNA. A logic low (<1.0V) selects the bypass mode. A logic high (>2.0V) turns on the LNA.
Preliminary
Interface Schematic
LNA GAIN
2
MIX GAIN
Controls the bypass feature of the mixer pre-amp. A logic low (<1.0V) selects the bypass mode. A logic high (>2.0V) turns on the pre-amp. LNA input pin.
MIX GAIN
3
LNA IN
LNA OUT
LNA IN
GND1B
4 5
VCC1 GND1B
VCC pin for all circuits except the LO. Buffer/bias circuitry. LNA emitter. This pin provides the DC path to ground for the LNA. A lumped element or a transmission line inductor can be placed between this pin and ground to degenerate the LNA. This will decrease the gain, increase the IP3, and increase the NF of the LNA. As the value of inductance is increased, these effects will become more pronounced. LNA output pin. An external resistor R2 connected to this pin sets the current of the preamp and the mixer. An external resistor R3 connected to this pin sets the current of the LNA when IP SET is high (see pin 19). Ground pin for pre-amp circuit. A 3.3nH inductor is used between pin 9 and ground to degenerate the mixer pre-amp. Degenerating the preamp will reduce the gain, increase the IP3 and affect the pre-amp input impedance.
MIX IN
6 7
LNA OUT ISET2 ISET1 GND3B
See pin 3.
8
FRONT-ENDS
8 9
VCC2
GND3B
10 11 12
MIX IN IF1IF1+
Mixer pre-amp input pin. Second differential output pin for the first mixer. First differential output pin for the first mixer. Open collector. A current combiner external network performs a differential to single-ended conversion and sets the output impedance. A DC blocking cap must be present if the IF filter input has a DC path to ground. Mixer (IF2+ and IF-) needs to "see" a differential impedance between 2k to 4k.
See pin 9. See pin 12.
IF1IF1+
13 14
BYPASS IF2-
Bypass pin for the LO bias reference. Second differential output pin for the second mixer. See pin 15.
8-126
Rev A13 010607
Preliminary
Pin 15 Function IF2+ Description
First differential output pin for the second mixer. Open collector. A current combiner external network performs a differential to single-ended conversion and sets the output impedance. A DC blocking cap must be present if the IF filter input has a DC path to ground. Mixer (IF2+ and IF2-) needs to "see" a differential impedance between 2k to 4k.
RF2461
Interface Schematic
IF2IF2+
16 17
VCC2 LO IN
VCC pin for the LO buffer/bias circuitry.* LO limiter input pin.
LO IN
18
ENABLE
This pin is used to enable or disable the RF2461. A logic high (>2.0V) enables the circuitry. A logic low (<1.0V) disables the circuitry.
ENABLE
19
IP SET
Controls the setting of the LNA current. A logic low (<1.0V) selects the internal resistance (49.5k), resulting in an LNA current of 5mA. A logic high (>2.0V) selects the external resistance at pin 8. Determines which IF port is active. A logic low (<1.0V) activates IF1 and deactivates IF2. A logic high (>2.0V) activates IF2 and deactivates IF1. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias.
IP SET
8
IF SEL
20
IF SEL
Pkg Base
GND
*The bias circuitry current drop when LO signal is not present. Total LO buffer/bias circuitry current is 7mA when LO signal is present.
Rev A13 010607
8-127
FRONT-ENDS
RF2461
Application Schematic
Preliminary
VCC2 NOTE: Microstrip Inductor, Z0 = 50 , L = 102 mils suggested compared values. 56 LO IN ENABLE IP SET IF SEL LNA GAIN 1 MIX GAIN 4.3 nH LNA IN 16 nH 33 nF 3 13 BYPASS 100 pF 4 100 pF VCC1 51 50 strip 5 L=130 mils W=12 mils Z0=50 11 L1 6 7 8 9 10 C1 0.1 F 100 pF 22 k 50 strip 7.5 nH 620 L2 Filter VCC1 4 pF 47 nH 100 pF 47 k 3.3 nH 33 nF L IF+ IFR C1 12 2 14 C1 20 19 18 17 16 L1 15 R C1 L Filter 100 pF L2 100 pF C2 IF2+ IF2VCC1
51 * VCC1
C2
8
FRONT-ENDS
*This resistor improves NF and IIP3 for VCC = 3.0 V.
Filter
Output Interface Network
L1, C1, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation:
fIF = 1
L1 2 (C1 + C EQ) 2
where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C1 should be chosen as high as possible (not greater than 15pF), while maintaining an RP of L1 that allows for the desired ROUT. L2 and C2 serve dual purposes. L2 serves as an output bias choke, and C2 serves as a series DC block. In addition, L2 and C2 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large, and C2 is chosen to be large if a DC path to ground is present in the IF filter, or omitted if the filter is DC blocked.
Where CEQ is the equivalent stray capacitance and capacitance looking into pins 11 and 12. An average value to use for CEQ is 2.5pF to 3pF. R can then be used to set the output impedance according to the following equation:
R= 1 (4 R
-1
OUT
RP
) -1
8-128
Rev A13 010607
Preliminary
Evaluation Board Schematic - CDMA LO@965MHz, RF@880MHz, IF@85MHz
(Download Bill of Materials from www.rfmd.com.)
P1 P1-1 1 2 P1-3 3 CON3 ENABLE IP SET IF SEL 20 LNA GAIN 1 MIX GAIN 329 pS Electrical Delay 0.10 dB Line Loss J2 LNA IN 50 strip 2 50 strip L1 4.3 nH L2 16 nH C1 33 nF 4 C2 100 pF VCC1 R14 51 50 strip 5 L=130 mils W=12 mils Z0=50 11 50 strip L6 470 nH R4 10 k 12 50 strip 3 13 50 strip 14 15 19 18 17 16 50 strip MIX GAIN GND LNA GAIN P2-1 P2-2 P2-3 P2 1 2 3 CON3 IF SEL IP SET ENABLE P3-3 P3-1 P3 1 2 3 CON3 50 strip 50 strip L9 470 nH R5 10 k 50 strip VCC1 GND VCC2 447 pS Electrical Delay 0.13 dB Line Loss J1 LO IN R6 56 50 strip C16 100 pF L8 390 nH
RF2461
VCC2 VCC1 C15 100 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J6 IF2 OUT 50 strip
C14 11 pF
C13 10 pF
C12 11 pF BYPASS C11 100 pF
C10 11 pF
6
7
8
9
10
R14 51 VCC1 498 pS Electrical Delay 0.15 dB Line Loss J3 LNA OUT 50 strip Note: R14 improves NF and IIP3 for VCC = 3.0 V
C3 0.1 F
C4 100 pF L4 7.5 nH C5 4 pF R1 620 50 strip
50 strip R2 18 k R3 47 k L4 3.3 nH 50 strip L7 390 nH C7 100 pF 50 strip C6 33 nF 50 strip L5 47 nH
C9 10 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J5 IF1 OUT 50 strip VCC1
C8 11 pF
8
FRONT-ENDS
50 strip
320 pS Electrical Delay @ 880 MHz 0.10 dB Line Loss J4 MIXER IN
Rev A13 010607
8-129
RF2461
Preliminary
Evaluation Board Schematic - JCDMA LO@741MHz, RF@851MHz, IF@110MHz
P1 P1-1 1 2 P1-3 3 CON3 ENABLE IP SET IF SEL MIX GAIN GND LNA GAIN P2-1 P2-2 P2-3
P2 1 2 3 CON3 IF SEL IP SET ENABLE P3-3 P3-1
P3 1 2 3 CON3 VCC1 GND VCC2
447 pS Electrical Delay 0.13 dB Line Loss J1 LO IN R6 56 50 strip C16 100 pF L8 270 nH C15 100 pF
VCC2 VCC1
50 strip 50 strip 20 19 18 17 16 50 strip 1 15
50 strip C14 7 pF L9 330 nH R5 4.3 k
348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J6 IF2 OUT 50 strip
LNA GAIN
C13 9 pF
MIX GAIN 329 pS Electrical Delay 0.10 dB Line Loss J2 LNA IN 50 strip 2 50 strip L1 4.3 nH L2 16 nH C1 33 nF 4 C2 100 pF VCC1 R14 51 50 strip 5 L=130 mils W=12 mils Z0=50 11 50 strip L6 330 nH R4 4.3 k C9 9 pF 12 50 strip 3 13 50 strip 14
C12 10 pF BYPASS C11 100 pF
C10 11 pF
6
7
8
9
10
R14 51 VCC1 498 pS Electrical Delay 0.15 dB Line Loss J3 LNA OUT 50 strip Note: R14 improves NF and IIP3 for VCC = 3.0 V
C3 0.1 F
C4 100 pF L4 7.5 nH C5 4 pF R1 620 50 strip
50 strip R2 18 k R3 33 k L4 7.5 nH 50 strip L7 270 nH C7 100 pF 50 strip 50 strip L5 30 nH
C8 7 pF
348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J5 IF1 OUT 50 strip VCC1
8
FRONT-ENDS
50 strip
C6 33 nF
320 pS Electrical Delay @ 880 MHz 0.10 dB Line Loss J4 MIXER IN
8-130
Rev A13 010607
Preliminary
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.031", Board Material FR-4, Multi-Layer
Assembly Top
RF2461
8
Power Plane 1 Power Plane 2
FRONT-ENDS
Rev A13 010607
8-131
RF2461
Back
Preliminary
8
FRONT-ENDS
8-132
Rev A13 010607
Preliminary
LNA Gain, Noise Figure and IIP3 versus ICC 16.0
RF2461
Mixer Gain, Noise Figure and IIP3 versus ICC 15.0 25.00 20.00 10.0 15.00 5.0 5.00
LNA Only (LNA High Gain)
Mixer (Mixer High Gain, LO=-7dBm)
10.00
14.0
Gain and Noise Figure (dB)
Gain and Noise Figure (dB)
12.0
10.00 5.00 0.00 0.00 -5.00 -10.00 -5.00 Gain (dB) NF (dB) -15.00 IIP3 (dBm) -10.00 40.00
10.0
IIP3 (dBm)
0.0 8.0 -5.0 6.0 Gain (dB) NF (dB) 4.0 IIP3 (dBm) -15.0 -10.0
2.0
0.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
-20.0 16.0
-20.00 10.00
15.00
20.00
25.00
30.00
35.00
ICC (mA)
ICC (mA)
200.0 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0.0 2.0
Resistor (R3) versus ICC (mA) LNA Only (LNA High Gain)
R3 (kohm)
200.0 180.0 160.0 140.0
Resistor (R2) versus ICC - Mixer (Mixer High Gain, LO=2170@-7dBm)
R2 (kohm)
IIP3 (dBm)
8
FRONT-ENDS
15.0 20.0 25.0 30.0 35.0 40.0
Resistor R2 ( k )
4.0 6.0 8.0 10.0 12.0 14.0 16.0
Resistor R3 (k )
120.0 100.0 80.0 60.0 40.0 20.0 0.0 10.0
ICC (mA)
ICC (mA)
Condition T=25oC, VCC=2.75V, RF=880 and 881MHz, LO=965MHz @-10dBm
IP_SET MIXER_GAIN LNA_GAIN1 LNA_GAIN2
0 1 1
IF_SEL
0 0 0
LNA GAIN MIX GAIN
0 0 1 1 0 0
ENABLE
1 1 1
LNA Current=LNA Gain2-LNA-Gain1
Rev A13 010607
8-133
RF2461
LNA (Low Gain Mode)
1.00 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -6.00 -5.00 -7.00 -8.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3 -10.00 2.7 2.8 2.9 3.0 S21, -30 S21, 25 S21, 85 10.00 15.00 20.00
Preliminary
LNA (Low Gain Mode)
IIP3 (dBm)
S21 (dB)
5.00
0.00
IIP3, -30 IIP3, 25 IIP3, 85
3.1
3.2
3.3
VCC (V)
VCC (V)
LNA (High Gain/Low IP Mode)
15.10 15.00 13.00 14.00
LNA (High Gain/Low IP Mode)
8
FRONT-ENDS
S21 (dB)
14.90 14.80 12.00
IIP3 (dBm)
14.70 14.60 14.50 14.40 14.30 14.20 14.10 2.7 2.8 2.9 3.0 3.1 3.2 3.3 S21, -30 S21, 25 S21, 85
11.00
10.00
9.00 IIP3, -30 8.00 IIP3, 25 IIP3, 85 7.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3
VCC (V)
VCC (V)
LNA (High Gain/Low IP Mode)
2.40 NF, -30 2.20 NF, 25 NF, 85 14.90 2.00 14.80 15.00 15.10
LNA (High Gain/High IP Mode)
S21, -30 S21, 25 S21, 85
S21 (dB)
2.7 2.8 2.9 3.0 3.1 3.2 3.3
NF (dB)
1.80
14.70 14.60 14.50
1.60
1.40 14.40 1.20 14.30 1.00 14.20 2.7 2.8 2.9 3.0 3.1 3.2 3.3
VCC (V)
VCC (V)
8-134
Rev A13 010607
Preliminary
LNA (High Gain/High IP mode)
15.00 2.40 NF, -30 14.00 2.20 NF, 25 NF, 85 13.00 2.00
RF2461
LNA (High Gain/High IP Mode)
IIP3 (dBm)
11.00
NF (dB)
IIP3, -30 IIP3, 25 IIP3, 85 2.7 2.8 2.9 3.0 3.1 3.2 3.3
12.00
1.80
1.60
10.00
1.40
9.00
1.20
8.00
1.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3
VCC (V)
VCC (V)
VCC versus ICC, LNA High Mode, Low IP
25.50 Icc, -30 25.00 24.50 24.00 23.50 23.00 22.50 22.50 22.00 21.50 21.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3 22.00 21.50 21.00 2.7 Icc, 25 Icc, 85 25.50 25.00 24.50 24.00 26.00
VCC versus ICC, LNA High Mode, High IP
Icc, -30 Icc, 25 Icc, 85
8
FRONT-ENDS
ICC (mA)
ICC (mA)
23.50 23.00
2.8
2.9
3.0
3.1
3.2
3.3
VCC (V)
VCC (V)
Mixer (IF1), Low Gain Mode, LO@-10dBm
7.00 Gain, -30 6.80 6.60 6.40 Gain, 25 Gain, 85 14.50 15.00 15.50
Mixer IF1, Low Gain Mode, LO@-10dBm
IIP3, -30 IIP3, 25 IIP3, 85
IIP3 (dBm)
Gain (dB)
6.20 6.00 5.80 5.60 5.40
14.00
13.50
13.00
12.50 5.20 5.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3 12.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3
VCC (V)
VCC (V)
Rev A13 010607
8-135
RF2461
Mixer IF1, Low Gain Mode, LO@-10dBm
14.00 16.00
Preliminary
Mixer IF1, High Gain Mode, LO@-10dBm
13.50 15.50 13.00 Gain, -30 12.50
Gain (dB)
15.00
Gain, 25 Gain, 85
NF (dB)
12.00
11.50
14.50
11.00 NF, -30 10.50 NF, 25 NF, 85 10.00 2.7 2.8 2.8 2.9 2.9 3.0 3.0 13.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 14.00
VCC (V)
VCC (V)
Mixer IF1, High Gain Mode, LO@-10dBm
5.00 8.50 8.00 4.50
Mixer IF1, High Gain Mode, LO@-10dBm
NF, -30 NF, 25
8
4.00
7.50 7.00
NF, 85
FRONT-ENDS
IIP3 (dBm)
NF (dB)
IIP3, -30 IIP3, 25 IIP3, 85 2.7 2.8 2.9 3.0 3.1 3.2 3.3
6.50 6.00 5.50 5.00 4.50 4.00 2.75
3.50
3.00
2.50
2.00
2.80
2.85
2.90
2.95
3.00
VCC (V)
VCC (V)
Mixer IF1, High Gain Mode, VCC@2.75V
16.00 4.50
Mixer IF1, High Gain Mode, VCC@2.75V
15.50 4.00 Gain, -30 15.00 Gain, 25
14.50
IIP3 (dBm)
Gain (dB)
Gain, 85
3.50
3.00
14.00
2.50 13.50
IIP3, -30 IIP3, 25 IIP3, 85
13.00 -10.0
-8.0
-6.0
-4.0
-2.0
0.0
2.00 -10.0
-8.0
-6.0
-4.0
-2.0
0.0
LO (dBm)
LO (dBm)
8-136
Rev A13 010607

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